The present disclosure generally relates to an I/O circuit and, more particularly, to a high voltage tolerant I/O circuit for an electronic device.
In many electronic devices, an internal chip is typically designed to have an actual operating voltage lower than a nominal operating voltage of the electronic device. For example, the nominal operating voltage of some electronic devices is 5V, but the actual operating voltage of the internal chip is designed to be only 3.3V, or even lower to 1.1V. The reliability of the I/O circuit in the electronic device seriously affects the durability of the electronic device. Accordingly, an additional protection circuit is typically employed in the traditional I/O circuit to avoid the internal chip of the electronic device from damaging by an external voltage transmitted from a signal pad of the electronic device.
The protection circuit in the traditional I/O circuit operates according to an internal operating voltage generated by the internal chip of the electronic device. However, in some applications (such as the electronic devices using HDMI, I2C, or USB I/O interfaces), the core voltage of the internal chip and the internal operating voltage provided from the internal chip to the I/O circuit would be completely turned off when the internal chip needs not to operate. In this situation, the protection circuit in the I/O circuit is unable to operate. At this time, if the signal pad of the electronic device is still coupled with the external high voltage signal terminal, the external voltage received at the signal pad may easily damage the I/O circuit and the internal chip of the electronic device, thereby causing the electronic device to be malfunction or be damaged.